JTAG muxes and multidrop


There are devices that provide access to multiple scan chains. These typically provide two levels of multiplexing. Second, a number of multdrop chips are wired in parallel on the backplane. Second, each device typically provides a number of TAP ports that can be switched into the chain.Some of the others basically appear in the JTAG chain and control data is shifted into the instruction register. Until a device on the backplane bus has been selected, TDO is tristate. The linking shadow protocol is less consistent, perhaps, with JTAG philosophy but it could be advantagous when using software that doesn't understand port multiplexors as a utility program can be used to configure the multiplexor(s) and then the presence of the multiplexor is invisible to the software (provided it does not wiggle TDI in states where it is inappropriate to do so). Some multiplexors also have the ability for one of the slave ports to take over a master. This allows an embedded CPU to perform built in self test or reconfiguration while still allowing external test. Many of the multiplexors also allow the JTAG slave ports to be tristated allowing an external JTAG tester to be connected.

JTAG Details


A JTAG Test Access Port (TAP) consists of 4 signals, with an optional fifth signal:

  • TMS - Test Mode Select (input from controller) (pullup required to force entry into reset state in event of a bad connection on TMS).
  • TCK - Test Clock (input from controller)
  • TDI - Test Data In (input from controller)
  • TDO - Test Data Out (output to controller or next chip in chain)
  • TRST* - Test Reset (optional, input from controller)

Some JTAG ports have some additional non-standard signals. Microcontrollers often have a debug enable signal that switches between normal JTAG mode and OCD mode. Some ports have a RTCK signal which echos the TCK signal. In many cases TCK is tied to RTCK at the JTAG connector and this may be used to adjust for cable delay. On some ARM7TDMI based chips, this is used to synchronize TCK to the internal system clock. Thus the idea is for the JTAG pod to assert an edge on TCK and wait for the processor to return that edge on RTCK before proceeding. The philips LPC2468 microntroller has RTCK but the Ateml AT91SAM7XC256 does not, though both use the ARM7TDMI core. Many ports have a SRST signal, to reset the processor and other logic. It may also indicate to a debugger that the processor has been manually reset. Some processors have a separate reset input and reset output. Other processors will pull their reset line low when an internal reset is generated. This is a smarter design as it not only saves a pin but it allows one or more chips to hold the system reset low. On the LPC2400 family, RSTOUT is a 1.8V output while JTAG pins are 5V tolerant 3.3V signals, presenting level translation issues if one were to attempt to read this signal. Most JTAG interface connectors have a Vcc/Vdd/Vref pin that is used to adjust the level translators to the appropriate voltage level for the system. In addition, many JTAG interfaces have a system reset line; you may want to sense the state of that line to signal a debugger when a chip has been reset. You may also want to measure the presence of Vref. Since some systems use the JTAG pins for other purposes as well, you may want to tristate the outputs. The voltage level varies depending on the technology being used. Multiple chips (or even boards) with JTAG support can be chained together with the TDO of each chip connected to the TDI of the next. The remaining signals are connected in parallel. Timing is based on the TCK pin so a PC parallel port (with appropriate voltage translation if needed) can be used as a controller. TDI/TMS data is latch on the rising edge of TCK. TDI/TDO/TMS typically change on the falling edge of TCK. You could probably do a full synchronous implementation where the data changes on the rising edge but you would have to be carefull with cable skew and hold types.
Note that the idea of having a TRST line may be less so the pod can reset the TAP controller, which is unnecessary since 5 TCKs with TMS high will accomplish the same result, and more so the board design can pull TRST low through a low value pull-down resistor which the POD can override. Thus, it may be necessary to implement TRST even if you have no need to use it.
In addition, some microcontrollers have a trace port (called ETM on ARM7TDMI). Since the internal address and databus are not usually brought out to pins the trace port can be used to monitor the flow of program execution. On the ARM7TDMI, this is about 8 signals clocked out at the CPU clock rate. By decoding those signals, you can tell when the next instruction in sequence has been executed and when a branch has been taken. A debugger with access to a copy of the code loaded into the micro, a which thus knows the size of each instruction and the destination of each branch can map the flow. Interrupts, however, could complicate this. On ARM7TDMI, a low on RTCK during reset may enable the ETM port. The ETM is configured through the JTAG interface. Use of ETM involves giving up some I/O lines.


Registers





A JTAG device contains multiple registers or chains accessable via the TAP port. If the TAP controller is in the Shift-IR state, the instruction register will be used. In the Shift-DR, the register inserted into the chain will depend on the currently active instruction in the instruction register.

Standard Data Registers

In addition, to the instruction register, each device has more than one data register. At any given time, data is shifted though either the instruction register or one of the data registers depending on the state of the TAP controller and the last instruction loaded. Registers are shifted LSB first.
The boundary-scan register (required)

The boundary-scan register typically contains one or more bits for each logic pin on the device. More than one bit is needed to deal with output enables and direction controls for some pins. All device inputs must be observable and all device outputs controllable through the boundary scan register. The register may provide access to internal states associated with each pin.
The bypass Register (required)

This is a single bit wide shift register connecting TDI and TDO. It is selected in bypass mode and is used to minimize the number of bits that need to be shifted when accessing other chips. Why a one bit delay? Without it, you would end up with an analog delay in TDI proportional to the number of chips and under some conditions, TCK would get there before TDI would.
Device ID register (optional)

This is a 32 bit register that contains information that can be used to identify the specific chips in the chain.