Samsung has published new research showing a way to cut NAND flash power consumption by a large margin. In a paper released in Nature, a team of 34 engineers from Samsung's Advanced Institute of Technology (SAIT) and the Semiconductor R&D Center describes how combining ferroelectric materials with oxide semiconductors can reduce power use during string-level operations (the method by which NAND flash reads/writes data by passing signals through series-connected cells) by up to 96%. Modern NAND keeps adding more layers to increase capacity, but this also lengthens the path that signals have to travel through each string of cells. As the stack gets taller, read and write power goes up. Earlier attempts to use ferroelectric designs didn't fully solve this problem. Samsung's approach takes advantage of the electrical characteristics of oxide semiconductors. These materials normally have limited threshold-voltage control, which is seen as a drawback in other device types. In this design, however, that behavior helps lower switching power while still supporting high density, including up to 5 bits per cell. By reworking the transistor structure and applying these materials in a NAND layout, the team shows a clear path to much lower power consumption without sacrificing storage capacity.

If brought to market, the technology could help reduce power use in data centers and improve battery life in mobile and edge-AI devices. Market research firm Omdia projects global NAND revenue will jump from $65.6 billion in 2024 to $93.7 billion in 2029 with shipments growing at an average rate of 17.7% annually over that period. However, just last week we reported that the company seems to plan converting parts of its NAND flash lines in Pyeongtaek and Hwaseong into DRAM production, and will also run its upcoming Pyeongtaek Fab 4 (P4) as a DRAM-only line. Industry sources say Samsung has become cautious about the NAND market, while demand (and prices) for standard DRAM have jumped sharply.

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